Starkey Engineers win 'Best Design Paper' at the 2004 Design and Verification Conference (DVCon) in San Jose, California

Bill Dittenhofer and Dr. Greg Tumbush of Starkey Laboratories' IC Design Center in Colorado Springs, Colorado were awarded "Best Design Paper" for their paper titled "Design and Verification of a Processor Using VHDL, Verilog, System C and C++."

Starkey President, Jerry Ruzicka said, "It's a great honor for Starkey's IC development team to be recognized for their hard work and broad contribution to the company's technology base. Integrated circuits, semiconductor research and software algorithms utilized in Starkey's current product lines reflect the talent and dedication of our entire engineering staff."

DVCon 2004 was held March 1-3 in San Jose, California and featured 48 submitted papers for review, peer tutorials and panel discussions. The conference presents awards for the "Best Design" and "Best Verification" papers chosen by attendees.

DVCon is the premier conference on the usage of Hardware Description Languages, and Hardware Verification Languages for the design and verification of electronic systems and integrated circuits. The focus of the conference is on specialized languages such as VHDL, PSL, Verilog, SystemVerilog, SystemC, SUPERLOG, e and VERA, as well as general purpose languages such as C and C++. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation tools.

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